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pdsp16340 1 pdsp16340 polar to cartesian converter features the pdsp16340 can be configured to perform either a coordinate conversion function, or simply to provide a sine / cosine look-up table. when employed as a coordinate conver- sion processor, the device converts data from 16 bit polar coordinates (r,) into 16 bit cartesian coordinates (real, imaginary). the translation is illustrated in fig. 1, and uses the formula:- xr = r cos() xi = r sin() in look-up table mode, the user enters 16 bit phase data, and the chip outputs the corresponding sine and cosine values. a typical application is shown in fig. 5. the pdsp16340 is pipelined to process a continuous stream of data at 20 mhz, and outputs a new (16 + 16) bit result every clock cycle. the range control signal allows the user to select the input range most appropriate to the system. data is produced in two? complement fractional format. applications pdsp16330 pythagoras processor pdsp16256 programmable fir filter pdsp16510 fft processor pdsp16350 i/q splitter and nco pdsp16116 16 bit complex multiplier pdsp16318 complex accumulator cordic processor array real (cosine) imaginary (sine) magnitude adjust phase magnitude associated products digital signal processing radar systems sonar systems robotics medical imaging fig. 1. cartesian to polar coordinates fig. 2. simplified block diagram provides r cos() and r sin() in 16 bit streams using a cordic processor look-up table equivalent to 64k by 32 bit rom 20mhz clock rate tri-state outputs and independent data enables 84 pin pga or 132 pin qfp ds3710 - 2.1 r imaginary real x x i r advance information (supersedes version in december 1993 digital video & digital signal processing ic handbook, hb3923-1) february 1995
pdsp16340 2 pen mode m1 m3 m5 vdd m8 gnd m10 m12 m14 vout sat range m0 m2 m4 m6 m7 m9 m11 m13 m15 vin p15 o/c xi15 xi14 p13 p14 xi13 xi12 p11 p12 xi11 xi10 gnd p10 xi9 gnd p9 p8 xi8 xi7 vdd p7 xi6 vdd p6 p5 xi4 xi5 p4 p3 xi2 xi3 p2 p1 xi0 xi1 p0 xr15 xr13 xr11 xr9 xr7 xr6 xr4 xr2 xr0 men clock gnd xr14 xr12 xr10 vdd xr8 gnd xr5 xr3 xr1 oei oer 12345678910111213 a b c d e f g h j k l m n fig. 3a device pinout - bottom view (84 pin pga - ac84)
pdsp16340 3 gc 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 sig n/c men n/c xi0 xi1 xi2 gnd vdd xi3 xi4 n/c xi5 xi6 n/c xi7 xi8 vdd gnd xi9 n/c xi10 xi11 n/c xi12 xi13 xi14 vdd gnd xi15 vin n/c n/c sat gc 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 sig n/c vout m15 gnd vdd m14 n/c m13 m12 n/c m11 m10 n/c m9 gnd vdd m8 m7 m6 m5 vdd m4 vdd m3 gnd m2 m1 gnd vdd m0 mode pen vdd gc 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 sig gnd range n/c n/c p15 gnd vdd p14 p13 p12 n/c p11 p10 n/c p9 gnd vdd p8 p7 p6 n/c p5 n/c p4 p3 vdd gnd p2 p1 n/c p0 n/c clk gc 100 101 102 103 104 105 106 107 108 109 110 111 112 113 114 115 116 117 118 119 120 121 122 123 124 125 126 127 128 129 130 131 132 sig gnd vdd gnd n/c xr15 xr14 n/c xr13 xr12 n/c xr11 n/c xr10 xr9 vdd gnd xr8 xr7 n/c xr6 xr5 n/c xr4 n/c xr3 xr2 n/c xr1 vdd gnd xr0 oe1 oe2 fig.3b pin out table (132 pin ceramic qfp - gc132)
pdsp16340 4 signal description m15:0 16 bit 2's complement data representing the magnitude of the phase angle. data is loaded into the input register on the rising edge of clk. these inputs are not used in look-up table mode, however, they should be tied high or low for electrical, rather than logical, reasons. m15 is the msb. p15:0 16 bit data representing the phase angle. data is loaded into the input register on the rising edge of clk. p15 is the msb. xr15:0 16 bit 2? complement real data output, or cosine output in the table look-up mode. data is passed to the xr outputs on the rising edge of clk. xi15:0 16 bit 2? complement imaginary data output, or sine output in the table look-up mode. data is passed to the xi outputs on the rising edge of clk. range magnitude range select. when this pin is high, the msb of the m input bus (also the sign bit) will represent 2 1 . when low, it will represent 2 0 sat input data saturated flag. this output goes high to indicate that input data of magnitude greater than sqrt(2) has been saturated to sqrt(2). it is internally delayed such that it appears at the output at the same time as the data which resulted from the saturated input value. men clock enable for the magnitude input port. when low new data may be latched in the input register; when high the register remains in its previous state. pen clock enable for the phase input port. when low new data may be latched in the input register: when high the register remains in its previous state. oer output enable for the xr output port. when high the xr output is forced into a high impedance state. oei output enable for the xi output port. when high the xi output is forced into a high impedance state. vin valid data input flag. this input is connected to vout via a pipeline delay which matches the data path pipeline delay. hence, if vin is set high when valid data is input, then vout will go high when valid results are output. it performs no internal control function. vout valid data output flag which is a delayed version of vin as explained above. mode when high, this input configures the chip into look-up table mode in which the m inputs are redundant and internally replaced by a unity magnitude. when low, the chip is configured in coordinate conversion mode. clk common clock to all internal registers. vdd four +5v power pins. all power supply pins must be connected. gnd four ground pins. all pins must be connected. table 1. signal description
pdsp16340 5 operation the functional blocks used within the device are illus- trated by fig. 4. both input data and output data are fully registered to allow the device to be easily incorporated into data flow dsp systems. the sine and cosine values are actually calculated in a 26 stage pipelined arithmetic proces- sor, and are accurate to 16 bits. this technique allows high data throughputs, and requires less die area than the equiva- lent rom. the pdsp16340 has two modes of operation, which are selected by the logical state of the mode input pin. this pin should be tied high or low to suite the particular application. look-up mode in the table look-up mode the mode pin is tied high, and the device is used to provide simultaneous sine and cosine values at rates up to the maximum clock frequency. a new phase value is clocked into the phase port (p15:0) on each cycle, and the corresponding sine and cosine values appear at the xi and xr ports 29 clock cycles later. in this operating mode the magnitude inputs, the men , and the range inputs are logically redundant. they must, however, be tied either high or low for electrical reasons. if the phase port is disabled by pulling pen high, then the look-up table will continue to provide the sine and cosine outputs corresponding to the value of p15:0 present during the active clock edge before the pen level change. fig. 4. internal block diagram cordic processor array xr15:0 xi15:0 delay select sat unity magnitude adjust and saturate at sqrt(2) delay vout p15:0 m15:0 vin pen mode men range oei oer fig. 5. illustrates a typical fft arrangement with the pdsp16340 providing sine and cosine ?widdle?factors for use by the butterfly processor. use of the pdsp16520 quad port ram, and the pdsp16116 / 318 complex arithmetic element, allows butterfly calculations to be performed at rates up to 20?hz. coordinate conversion in the coordinate conversion processor mode the mode pin is tied low, and the pdsp16340 converts data from polar format into the corresponding real and imaginary cartesian co-ordinates. the coordinate conversion operation is equiva- lent to the inverse of the function performed by the pdsp16330 pythagoras processor. the device produces simultaneous sine and cosine values from the incoming phase angle, and then multiplies these results with the appropriate magnitude value. the men input allows the value in the input latch to be retained in a similar manner to the use of the pen control. the range control allows the device to accept magni- tude data in the range of, either, -1 to within one lsb of +1, or from -2 to within one lsb of +2. the smaller range option allows maximum accuracy to be preserved, if fractional inputs are expected.the latter option enables the theoretical maxi- mum polar magnitude of sqrt(2) to be accommodated. a negative magnitude introduces a 180 phase shift.
pdsp16340 6 pdsp16520 data ram pdsp16520 data ram address generator pdsp16340 xi15:0 xr15:0 m15:0 men mode gnd +5v ar br ai bi a'r b'r a'i b'i sine cosine pdsp16116 / 318 butterfly processor complex frequency domain result complex time domain input fig. 5. sin / cos generator for 20 mhz fft system the sign bit is provided to maintain compatibility with normal arithmetic procedures, but in most applications the value will always be positive. the sign bit could then be tied low, and the lower fifteen bits used to define the input. if a negative value is used this will introduce a 180 phase shift. when the mode pin is high the state of the range pin is irrelevant, and the magnitude is internally defined to be unity. the device will replace all incoming values above the square root of two with the maximum value. the sat output indicates when this replacement has internally occurred. the flag is delayed such that it is valid at the same time as the output data which was calculated from the saturated input. data formats when the device is configured in the co-ordinate conver- sion mode (mode pin is low), the magnitude (m) input bus can have one of the following data formats: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit number weighting range = 1 range = 0 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 2 2 2 2 2 2 2 2 2 2 2 2 2 2 -15 2 s s the phase port has the following data format: thus, for example : +90 (= - 270 ) = 0100000000000000 -180 (= +180 ) = 1000000000000000 -90 (= +270 ) = 1100000000000000 the 16 bit radius value is multiplied with the 16 bit internally generated sine and cosine values, to produce a 16 bit result. the range input controls the format of the output data as given below: 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 2 2 2 2 2 2 2 2 2 2 2 2 2 2 bit number weighting in ? radians -15 2 0 2 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 bit number weighting range = 1 range = 0 or mode = 1 0 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 2 2 2 2 2 2 2 2 2 2 2 2 2 2 2 -1 -2 -3 -4 -5 -6 -7 -8 -9 -10 -11 -12 -13 -14 2 2 2 2 2 2 2 2 2 2 2 2 2 2 -15 2 s s
pdsp16340 7 notes 1. exceeding these ratings may cause permanent damage. functional operation under these conditions is not implied. 2. maximum dissipation or 1 second should not be exceeded, only one output to be tested at any one time. 3. exposure to absolute maximum ratings for extended peri- ods may affect device reliablity. 4. vcc = max. outputs unloaded, clock freq = max. 5. cmos levels are defined as v ih = vcc - 0.5v v il = +0.5v 6. current is defined as negative into the device. 7. jc data assumes that heat is extracted from the top face of the package. absolute maximum ratings (note 1) supply voltage vcc -0.5v to 7.0v input voltage v in -0.5v to vcc + 0.5v output voltage v out -0.5v to vcc + 0.5v clamp diode current per pin i k (see note 2) 18ma static discharge voltage (hmb) 500v storage temperature t s -65 c to 150 c ambient temperature with power applied t amb military -55 c to +125 c industrial -40 c to 85 c junction temperature 150 c package power dissipation 3500mw thermal resistances junction to case jc 5 c/w electrical characteristics operating conditions (unless otherwise stated) commercial: t amb = -0 c to +70 c t j(max) = 95 c v cc = 5.0v 5% ground = 0v industrial: t amb = -40 c to +85 c t j(max) = 110 c v cc = 5.0v 10% ground = 0v military: t amb = -55 c to +125 c t j(max) = 150 c v cc = 5.0v 10% ground = 0v switching characteristics characteristic industrial military units conditions min. typ. max. min. typ. max. m15:0 or p15:0 setup to clock rising edge 15 - 15 - ns m15:0 or p15:0 hold after clock rising edge 4 - 4 - ns men or pen setup to clock rising edge 20 - 20 - ns men or pen hold after clock rising edge 0 - 0 - ns range setup to clock rising edge 15 - 15 - ns range hold after clock rising edge 8 - 8 - ns clock rising edge to all outputs valid 5 30 5 30 ns 30pf clock freq dc 20 dc 20 mhz clock high time 15 - 15 - ns clock low time 20 - 20 - ns oer,oei low to data valid - 20 - 20 ns see fig. 6 oer,oei high to data high impedance - 20 - 20 ns see fig. 6 pipeline delay vin to vout 28 28 28 28 clks vcc current (cmos inputs) - 430 - 450 ma see note 4 vcc current (ttl inputs) - 460 - 500 ma see note 4 characteristic output high voltage output low voltage input high voltage input low voltage input leakage current input capacitance output leakage current output s/c current min. 2.4 - 3.0 - -10 -50 10 max. - 0.4 - 0.8 +10 +50 250 conditions i oh = 4ma i ol = -4ma gnd < v in < v cc gnd < v out < v cc v cc = max units v v v v m a pf m a ma symbol v oh v ol v ih v il i in c in i oz i sc value typ. 10 static characteristics
pdsp16340 8 delay from output high to output high impedance test waveform - measurement level delay from output low to output high impedance h v 0.5v v 0.5v l 1.5v 0.5v 1.5v 0.5v delay from output high impedance to output low delay from output high impedance to output high v - voltage reached when output driven high v - voltage reached when output driven low h l fig. 6 tri-state delay measurement load. ordering information commercial (0 c to +70 c) pdsp16340 / c0 / ac (20mhz - pga) pdsp16340 / c0 / gc (20mhz - qfp) industrial (-40 c to +85 c) pdsp16340 / b0 / ac (20mhz - pga) pdsp16340 / b0 / gc (20mhz - qfp) military (-55 c to +125 c) pdsp16340 / a0 / ac (20mhz - pga) pdsp16340 / a0 / gc (20mhz - qfp) call for availability of high rel parts and mil 883c screening. v t dut 30pf 1.5k
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pdsp16340 12 headquarters operations gec plessey semiconductors cheney manor, swindon, wiltshire sn2 2qw, united kingdom. tel: (0793) 518000 fax: (0793) 518411 gec plessey semiconductors p.o. box 660017 1500 green hills road, scotts valley, california 95067-0017, united states of america. tel: (408) 438 2900 fax: (408) 438 5576 customer service centres france & benelux les ulis cedex tel: (1) 64 46 23 45 tx: 602858f fax : (1) 64 46 06 07 germany munich tel: (089) 3609 06-0 tx: 523980 fax : (089) 3609 06-55 italy milan tel: (02) 66040867 fax: (02) 66040993 japan tokyo tel: (03) 3296-0281 fax: (03) 3296-0228 north america integrated circuits and microwave products scotts valley, usa tel (408) 438 2900 fax: (408) 438 7023. hybrid products, farmingdale, usa tel (516) 293 8686 fax: (516) 293 0061. south east asia singapore tel: (65) 3827708 fax: (65) 3828872 sweden stockholm, tel: 46 8 702 97 70 fax: 46 8 640 47 36 united kingdom & scandinavia swindon tel: (0793) 518510 tx: 444410 fax : (0793) 518582 these are supported by agents and distributors in major countries world-wide. gec plessey semiconductors 1995 publication no. ds3710 issue no. 2.1 february 1995 this publication is issued to provide information only which (unless agreed by the company in writing) may not be used, applied or reproduced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. no warranty or guarantee express or implied is made regard ing the capability, performance or suitability of any product or service. the company reserves the right to alter without prior knowledge the specification, design or price of any product or service. information concerning possible methods of use is provided as a guide only and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user's responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. these products are not suitable for use in any medical products whose failure to perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to the company's conditions of sale, w hich are available on request.
www.zarlink.com information relating to products and services furnished herein by zarlink semiconductor inc. trading as zarlink semiconductor o r its subsidiaries (collectively zarlink ) is believed to be reliable. however, zarlink assumes no liability for errors that may appear in this publication, or for liabil ity otherwise arising from the application or use of any such information, product or service or for any infringement of patents or other intellectual property rights owned by third parties which may result from such application or use. neither the supply of such information or purchase of product or service conveys any license, either e xpress or implied, under patents or other intellectual property rights owned by zarlink or licensed from third parties by zarlink, whatsoever. purchasers of produc ts are also hereby notified that the use of product in certain ways or in combination with zarlink, or non-zarlink furnished goods or services may infringe patents or o ther intellectual property rights owned by zarlink. this publication is issued to provide information only and (unless agreed by zarlink in writing) may not be used, applied or re produced for any purpose nor form part of any order or contract nor to be regarded as a representation relating to the products or services concerned. the products, t heir specifications, services and other information appearing in this publication are subject to change by zarlink without notice. no warranty or guarantee express or implied is made regarding the capability, performance or suitability of any product or service. information concerning possible methods of use is provided as a guide onl y and does not constitute any guarantee that such methods of use will be satisfactory in a specific piece of equipment. it is the user s responsibility to fully determine the performance and suitability of any equipment using such information and to ensure that any publication or data used is up to date and has not been superseded. man ufacturing does not necessarily include testing of all functions or parameters. these products are not suitable for use in any medical products whose failure t o perform may result in significant injury or death to the user. all products and materials are sold and services provided subject to zarlink s conditions of sale which are available on request. purchase of zarlink s i 2 c components conveys a licence under the philips i 2 c patent rights to use these components in and i 2 c system, provided that the system conforms to the i 2 c standard specification as defined by philips. zarlink and the zarlink semiconductor logo are trademarks of zarlink semiconductor inc. copyright 2001, zarlink semiconductor inc. all rights reserved. technical documentation - not for resale for more information about all zarlink products visit our web site at

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